Verification of asynchronous logic circuit design using process algebra

Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya. Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan, 28(8-9):33-43, 1997. [doi]

Authors

Tomohiro Yoneda

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Atsufumi Shibayama

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Takashi Nanya

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