Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya. Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan, 28(8-9):33-43, 1997. [doi]
@article{YonedaSN97,
title = {Verification of asynchronous logic circuit design using process algebra},
author = {Tomohiro Yoneda and Atsufumi Shibayama and Takashi Nanya},
year = {1997},
doi = {10.1002/(SICI)1520-684X(199708)28:8<33::AID-SCJ5>3.0.CO;2-M},
url = {http://dx.doi.org/10.1002/(SICI)1520-684X(199708)28:8<33::AID-SCJ5>3.0.CO;2-M},
tags = {process algebra, algebra, logic, design},
researchr = {https://researchr.org/publication/YonedaSN97},
cites = {0},
citedby = {0},
journal = {Systems and Computers in Japan},
volume = {28},
number = {8-9},
pages = {33-43},
}