An AES crypto chip using a high-speed parallel pipelined architecture - researchr publication authors

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Seong-Moo Yoo, Deen Kotturi, W. David Pan, John Blizzard. An AES crypto chip using a high-speed parallel pipelined architecture. Microprocessors and Microsystems, 29(7):317-326, 2005. [doi]

This author has not been identified. Look up 'Seong-Moo Yoo' in GoogleThis author has not been identified. Look up 'Deen Kotturi' in GoogleThis author has not been identified. Look up 'W. David Pan' in GoogleThis author has not been identified. Look up 'John Blizzard' in Google

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