An AES crypto chip using a high-speed parallel pipelined architecture

Seong-Moo Yoo, Deen Kotturi, W. David Pan, John Blizzard. An AES crypto chip using a high-speed parallel pipelined architecture. Microprocessors and Microsystems, 29(7):317-326, 2005. [doi]

@article{YooKPB05,
  title = {An AES crypto chip using a high-speed parallel pipelined architecture},
  author = {Seong-Moo Yoo and Deen Kotturi and W. David Pan and John Blizzard},
  year = {2005},
  doi = {10.1016/j.micpro.2004.12.001},
  url = {http://dx.doi.org/10.1016/j.micpro.2004.12.001},
  tags = {architecture},
  researchr = {https://researchr.org/publication/YooKPB05},
  cites = {0},
  citedby = {0},
  journal = {Microprocessors and Microsystems},
  volume = {29},
  number = {7},
  pages = {317-326},
}