Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano. Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 148-149, IEEE, 2017. [doi]
@inproceedings{YoshidaUA17,
title = {Digital embedded memory scheme using voltage scaling and body bias separation for low-power system},
author = {Yusuke Yoshida and Kimiyoshi Usami and Hideharu Amano},
year = {2017},
doi = {10.1109/ISOCC.2017.8368840},
url = {https://doi.org/10.1109/ISOCC.2017.8368840},
researchr = {https://researchr.org/publication/YoshidaUA17},
cites = {0},
citedby = {0},
pages = {148-149},
booktitle = {International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017},
publisher = {IEEE},
isbn = {978-1-5386-2285-8},
}