Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano. Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 148-149, IEEE, 2017. [doi]

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