Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita. Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electronic Testing, 11(1):81-92, 1997. [doi]
@article{YotsuyanagiKK97,
title = {Synthesis of Sequential Circuits by Redundancy Removal and Retiming},
author = {Hiroyuki Yotsuyanagi and Seiji Kajihara and Kozo Kinoshita},
year = {1997},
doi = {10.1023/A:1008251901959},
url = {http://dx.doi.org/10.1023/A:1008251901959},
tags = {redundancy},
researchr = {https://researchr.org/publication/YotsuyanagiKK97},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {11},
number = {1},
pages = {81-92},
}