2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications

Chang-Hyo Yu, Hyo-Eun Kim, Sungho Shin, Kyeongryeol Bong, Hyunsuk Kim, Yoonho Boo, Jaewan Bae, Minjae Kwon, Karim Charfi, Jinseok Kim, Hongyun Kim, Myeongbo Shim, Changsoo Ha, Wongyu Shin, Jae-Sung Yoon, Miock Chi, Byungjae Lee, Sungpill Choi, Donghan Kim, Jeongseok Woo, Seokju Yoon, Hyunje Jo, Hyunho Kim, Hyun-Seok Heo, Young-Jae Jin, Jiun Yu, Jaehwan Lee, Hyunsung Kim, Minhoo Kang, Seokhyeon Choi, Seung-Goo Kim, Myung-Hoon Choi, Jungju Oh, Yunseong Kim, Haejoon Kim, Sangeun Je, Junhee Ham, Juyeong Yoon, Jaedon Lee, Seonhyeok Park, Youngseob Park, Jaebong Lee, Boeui Hong, Jaehun Ryu, Hyunseok Ko, Kwanghyun Chung, Jongho Choi, Sunwook Jung, Yashael Faith Arthanto, Jonghyeon Kim, Heejin Cho, Hyebin Jeong, Sungmin Choi, Sujin Han, Junkyu Park, Kwangbae Lee, Sung-il Bae, Jaeho Bang, Kyeong-Jae Lee, Yeongsang Jang, Jungchul Park, Sanggyu Park, Jueon Park, Hyein Shin, Sunghyun Park, Jinwook Oh. 2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 42-44, IEEE, 2024. [doi]

Abstract

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