Kaijian Yuan, Xingming Zhang 0002. Low power mapping optimization of loops for dual-Vdd CGRAs. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 682-685, IEEE, 2017. [doi]
Abstract is missing.