Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

Sigit Yuwono, Seok-Kyun Han, Giwan Yoon, Han-Jin Cho, Sang-Gug Lee. Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array. IET Circuits, Devices & Systems, 8(2):73-81, 2014. [doi]

@article{YuwonoHYCL14,
  title = {Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array},
  author = {Sigit Yuwono and Seok-Kyun Han and Giwan Yoon and Han-Jin Cho and Sang-Gug Lee},
  year = {2014},
  doi = {10.1049/iet-cds.2013.0175},
  url = {http://dx.doi.org/10.1049/iet-cds.2013.0175},
  researchr = {https://researchr.org/publication/YuwonoHYCL14},
  cites = {0},
  citedby = {0},
  journal = {IET Circuits, Devices & Systems},
  volume = {8},
  number = {2},
  pages = {73-81},
}