Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology

Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. In Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Röning, editors, 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019. pages 1-6, IEEE, 2019. [doi]

Abstract

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