Abstract is missing.
- Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI TechnologySomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-6 [doi]
- Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital FiltersLavanya Maddisetti, J. V. R. Ravindra. 1-6 [doi]
- How Diversity Affects Deep-Learning Side-Channel AttacksHuanyu Wang, Martin Brisfors, Sebastian Forsmark, Elena Dubrova. 1-7 [doi]
- Accelerating Transient Fault Injection Campaigns by using Dynamic HDL SlicingAhmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001. 1-7 [doi]
- HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoCMohammad Amir Mansoori, Mario R. Casu. 1-7 [doi]
- MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time RequirementsPhilipp Jungklass, Mladen Berekovic. 1-7 [doi]
- IEEE 802.11ad SC-PHY Layer Simulator: Performance in Real-world 60 GHz Indoor ChannelsJiri Blumenstein, Jiri Milos, Ladislav Polak, Christoph F. Mecklenbräuker. 1-4 [doi]
- A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOSSiyu Tan, Lars Sundström, Mattias Palm, Sven Mattisson, Pietro Andreani. 1-4 [doi]
- Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space ApplicationsAzam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg. 1-6 [doi]
- A Fault-Tolerant Time-Predictable ProcessorChristos Gkiokas, Martin Schoeberl. 1-6 [doi]
- Towards a Python-Based One Language Ecosystem for Embedded Systems AutomationZhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker. 1-7 [doi]
- Dual-Stage Phase UnwrappingBardia Barabadi, Matthew Gara, Ali Jooya, Amirali Baniasadi, Nikitas Dimopoulos. 1-7 [doi]
- An Analogue Baseband Chain for a Magnetic Tunnel Junction Based RF Signal DetectorRui Ma, Simon Buhr, Zoltán Tibenszky, Martin Kreißig, Frank Ellinger. 1-6 [doi]
- Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCsAyca Akkaya, Firat Celik, Yusuf Leblebici. 1-7 [doi]
- Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH CodesE. Kavvousanos, Vassilis Paliouras. 1-6 [doi]
- A Time-Based Control Scheme for Power Factor Correction Boost ConverterChristopher H. K. Jensen, Rasmus B. Lind, Jens Christian Hertel, Ahmed M. Ammar, Arnold Knott, Michael A. E. Andersen. 1-6 [doi]
- 1/f-Noise and Offset Cancellation for Rail-to-Rail Single-Slope ADCs in MEA ApplicationsLukas Straczek, Dominik J. Veit, Jürgen Oehm. 1-5 [doi]
- A New Interpretation to Groszkowski's EffectMostafa Jafari Nokandi, Sumit Pratap Singh, Aarno Pärssinen, Timo Rahkonen. 1-4 [doi]
- A 36 nW trimless voltage reference with low sensitivity to PVT variationsCalvin Maxsen, Pere Llimós Muntal, Gunnar Gudnason, Ivan H. H. Jørgensen. 1-5 [doi]
- Sphere Decoder for Massive MIMO SystemsDimitris Vordonis, Vassilis Paliouras. 1-6 [doi]
- A 300mV-Supply Standard-Cell-Based OTA with Digital PWM Offset CalibrationPedro Toledo, Orazio Aiello, Paolo Stefano Crovetti. 1-5 [doi]
- A Hardware Inference Accelerator for Temporal Convolutional NetworksRashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey. 1-7 [doi]
- Linearization of Active Transmitter Arrays in Presence of Antenna Crosstalk for 5G SystemsFeridoon Jalili, Martin H. Nielsen, Ming Shen, Ole K. Jensen, Jan H. Mikkelsen, Gert Frølund Pedersen. 1-5 [doi]
- Layout Optimization Techniques for $r_{g}$ and, $f_{max}$ of Cascode Devices for mm Wave ApplicationsRana A. Shaheen, Timo Rahkonen, Rehman Akbar, Janne P. Aikio, Alok Sethi, Aarno Pärssinen. 1-4 [doi]
- A 40-GHz Fully-Integrated CMOS-Based Biosensor Circuit with an On-Chip Vector Network Analyzer for Circulating Tumor Cells AnalysisTaiki Nakanishi, Shunya Murakami, Atsuki Kobayashi, Md. Zahidul Islam, Kiichi Niitsu. 1-7 [doi]
- A Real-Time Fast Ethernet Transceiver achieving Sub-ns Time SynchronizationSimon Buhr, Martin Kreißig, Frank Ellinger. 1-7 [doi]
- Semantic segmentation with inexpensive simulated dataJukka Peltomäki, Mengyang Chen, Heikki Huttunen. 1-6 [doi]
- On Applications of Configurable Approximation to Irregular VoltageToshinori Sato, Tomoaki Ukezono. 1-6 [doi]
- Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump TopologyJakob Kenn Toft, Ivan H. H. Jørgensen. 1-7 [doi]
- Single Burst Depth-Resolving Raman Spectrometer Based on a SPAD Array with an On-Chip TDC to Analyse Heterogenous Liquid SamplesJere Kekkonen, Ilkka Nissinen. 1-5 [doi]
- Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOIMikko Hietanen, Janne Aikio, Alok Sethi, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen. 1-4 [doi]
- A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural NetworksSteinar Thune Christensen, Snorre Aunet, Omer Qadir. 1-6 [doi]
- An Explicitly Parallel Architecture for Packet Processing in Software Defined NetworksHesam Zolfaghari, Davide Rossi, Jari Nurmi. 1-7 [doi]
- Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone AdderSomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-7 [doi]
- Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity ImprovementJere Rusanen, Mikko Hietanen, Alok Sethi, Timo Rahkonen, Aarno Pärssinen, Janne P. Aikio. 1-4 [doi]
- Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCsArthur Silitonga, Zhou Jiang, Nadir Khan, Jürgen Becker. 1-7 [doi]
- A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAMJohn Reuben, Dietmar Fey. 1-6 [doi]
- A 500mV, 118nW, ∑Δ-Modulator ADC for Audio Detection in 28 nm FD-SOIMarkus Mogensen Henriksen, Dennis Øland Larsen, Pere Llimós Muntal, Ivan H. H. Jørgensen. 1-6 [doi]
- Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN CloudPanu Sjövall, Arto Oinonen, Mikko Teuho, Jarno Vanne, Timo D. Hämäläinen. 1-5 [doi]
- Practical Stimulus Design for a Multi-Tone FitMarko Neitola. 1-7 [doi]
- End-to-End Approximation for Characterizing Energy Efficiency of IoT ApplicationsMohammadreza Nakhkash, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg. 1-6 [doi]
- Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-PropagationMark G. Arnold, Ed Chester, John R. Cowles, Corey Johnson. 1-6 [doi]
- An All-Digital Duty-Cycle Corrector for Parallel High-Speed I/O LinksNico Angeli, Klaus Hofmann. 1-6 [doi]
- Designing at Millimeter-Wave: Lessons from a Triple Coil Variable TransformerAlok Sethi, Rehman Akbar, Janne P. Aikio, Rana A. Shaheen, Aarno Pärssinen, Timo Rahkonen. 1-4 [doi]
- Instruction Extension of a RISC-V Processor Modeled with IP-XACTSaman Payvar, Esko Pekkarinen, Rafael Stahl, Daniel Mueller-Gritschneder, Timo D. Hämäläinen. 1-5 [doi]
- Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded SystemsRuben Vazquez, Ann Gordon-Ross, Greg Stitt. 1-7 [doi]
- An AFE for Catheter-Based IEGM sensing with Inverter-based SAR ADCYuchen Zhao, Haoming Chu, Bengt Källbäck, Yajie Qin, Zhuo Zou, Lirong Zheng 0001. 1-5 [doi]
- A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet ClassificationRicardo Núñez-Prieto, Pablo Correa Gómez, Liang Liu. 1-6 [doi]
- Two-Stage Internal DAC Mismatch Mitigation for a Continuous-Time Delta-Sigma ADCMarko Neitola. 1-7 [doi]
- Fast Fixed-point Bicubic Interpolation Algorithm on FPGAJanne Koljonen, Vladimir A. Bochko, Sami J. Lauronen, Jarmo T. Alander. 1-7 [doi]
- T-LINC Architecture with Digital Combination and Mismatch Correction in the ReceiverEmilio J. Martínez-Pérez, Feridoon Jalili, Ming Shen, Jan H. Mikkelsen, Ole K. Jensen, Gert Frølund Pedersen. 1-5 [doi]
- The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning ApplicationsAneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin. 1-7 [doi]
- HALib: Hardware Assertion Library for on-board verification of FPGA-based modules using HLSJulián Caba, F. Rincón, J. Barba, J. A. de la Torre, Julio Dondo, J. C. López. 1-7 [doi]
- Two-Step Pipeline SAR ADC with passive Charge Sharing between CascadesDmitry Osipov 0001, Aleksandr Gusev, Steffen Paul, Vitaly Shumikhin. 8138-8143 [doi]