Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors

Piotr Zajac, Melvin Galicia, Cezary Maj, Andrzej Napieralski. Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. Microelectronics Journal, 52:40-48, 2016. [doi]

Abstract

Abstract is missing.