A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links - researchr publication authors

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Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter. A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. In International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017. pages 1-6, IEEE, 2017. [doi]

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