A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links

Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter. A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. In International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017. pages 1-6, IEEE, 2017. [doi]

@inproceedings{ZazoLRS17,
  title = {A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links},
  author = {Jose Fernando Zazo and Sergio López-Buedo and Mario Ruiz and Gustavo Sutter},
  year = {2017},
  doi = {10.1109/RECONFIG.2017.8279770},
  url = {https://doi.org/10.1109/RECONFIG.2017.8279770},
  researchr = {https://researchr.org/publication/ZazoLRS17},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-3797-5},
}