Jindrich Zejda, Eduard Cerny. Gate-level timing verification using waveform narrowing. In Jean Mermet, editor, Proceedings EURO-DAC 94, European Design Automation Conference, Grenoble, France, September 19-22, 1994. pages 374-379, IEEE Computer Society, 1994. [doi]
@inproceedings{ZejdaC94,
title = {Gate-level timing verification using waveform narrowing},
author = {Jindrich Zejda and Eduard Cerny},
year = {1994},
doi = {10.1145/198174.198287},
url = {http://doi.acm.org/10.1145/198174.198287},
researchr = {https://researchr.org/publication/ZejdaC94},
cites = {0},
citedby = {0},
pages = {374-379},
booktitle = {Proceedings EURO-DAC 94, European Design Automation Conference, Grenoble, France, September 19-22, 1994},
editor = {Jean Mermet},
publisher = {IEEE Computer Society},
isbn = {0-89791-685-9},
}