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Gang Zeng, Hideo Ito. Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Transactions, 88-D(5):984-992, 2005. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Hybrid BIST for System-on-a-Chip Using an Embedded FPGA CoreGang Zeng, Hideo Ito. vts 2004: 355-360 [doi] Non-Intrusive Test Compression for SOC Using Embedded FPGA CoreGang Zeng, Hideo Ito. dft 2004: 413-421 [doi]
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