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A fast HDL model for full-custom FPGA verification

Kaixuan Zhang, Zhihua Feng, Hao Zhou. A fast HDL model for full-custom FPGA verification. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 989-992, IEEE, 2017. [doi]

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