Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

Jeff Zhang 0001, Zahra Ghodsi, Siddharth Garg, Kartheek Rangineni. Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators. IEEE Design & Test of Computers, 37(2):93-102, 2020. [doi]

Abstract

Abstract is missing.