Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng. FPGA-based efficient implementation of SURF algorithm. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 315-318, IEEE, 2017. [doi]
@inproceedings{ZhangHHZ17,
title = {FPGA-based efficient implementation of SURF algorithm},
author = {Ying Zhang and Yujie Huang and Jun Han and Xiaoyang Zeng},
year = {2017},
doi = {10.1109/ASICON.2017.8252476},
url = {https://doi.org/10.1109/ASICON.2017.8252476},
researchr = {https://researchr.org/publication/ZhangHHZ17},
cites = {0},
citedby = {0},
pages = {315-318},
booktitle = {12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017},
editor = {Yajie Qin and Zhiliang Hong and Ting-Ao Tang},
publisher = {IEEE},
isbn = {978-1-5090-6625-4},
}