Zhiyong Zhang, Lei Ju, Zhiping Jia. Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead. In Luca Fanucci, Jürgen Teich, editors, 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. pages 942-947, IEEE, 2016. [doi]
@inproceedings{ZhangJJ16, title = {Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead}, author = {Zhiyong Zhang and Lei Ju and Zhiping Jia}, year = {2016}, url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7459443}, researchr = {https://researchr.org/publication/ZhangJJ16}, cites = {0}, citedby = {0}, pages = {942-947}, booktitle = {2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016}, editor = {Luca Fanucci and Jürgen Teich}, publisher = {IEEE}, isbn = {978-3-9815-3707-9}, }