A 16-valued logic FPGA architecture employing analog memory circuit - researchr publication

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Renyuan Zhang, Mineo Kaneko. A 16-valued logic FPGA architecture employing analog memory circuit. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 718-721, IEEE, 2016. [doi]

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