He Zhang, Junzhan Liu, Kang Wang 0001, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao. A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. In 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021. pages 123-124, IEEE, 2021. [doi]
@inproceedings{ZhangL0FFBPLZ21,
title = {A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output},
author = {He Zhang and Junzhan Liu and Kang Wang 0001 and Yunqian Fan and Shufeng Fu and Jinyu Bai and Biao Pan and Yongpan Liu and Weisheng Zhao},
year = {2021},
doi = {10.1109/ICTA53157.2021.9661898},
url = {https://doi.org/10.1109/ICTA53157.2021.9661898},
researchr = {https://researchr.org/publication/ZhangL0FFBPLZ21},
cites = {0},
citedby = {0},
pages = {123-124},
booktitle = {2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021},
publisher = {IEEE},
isbn = {978-1-6654-1747-1},
}