A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output

He Zhang, Junzhan Liu, Kang Wang 0001, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao. A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. In 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021. pages 123-124, IEEE, 2021. [doi]

Abstract

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