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Ge Zhang, Zichu Qi, Weiwu Hu. A novel design of leading zero anticipation circuit with parallel error detection. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 676-679, IEEE, 2005. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Parallel Error Detection for Leading Zero AnticipationGe Zhang, Weiwu Hu, Zichu Qi. jcst, 21(6):901-906, 2006. [doi]
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