The following publications are possibly variants of this publication:
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- A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding PerformanceFei Wu 0005, Meng Zhang, Yajuan Du, Xubin He, Ping Huang, Changsheng Xie, Jiguang Wan. tecs, 16(5), 2017. [doi]
- REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performanceMeng Zhang, Fei Wu, Xubin He, Ping Huang, Shunzhuo Wang, Changsheng Xie. mss 2016: 1-13 [doi]
- A Hybrid Scheme of Reducing Read Latency in NAND Flash by Integrating Duplications and Soft DecodingYaofang Zhang, Peixuan Li, Ping Xie. icmlsc 2022: 151-159 [doi]
- Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash MemoryMeng Zhang 0014, Fei Wu 0005, Yajuan Du, Weihua Liu, Changsheng Xie. tcad, 38(12):2312-2320, 2019. [doi]
- A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND FlashLanlan Cui, Xiaojian Liu, Fei Wu 0005, Zhonghai Lu, Changsheng Xie. tcad, 41(6):1971-1975, 2022. [doi]