Junneng Zhang, Chao Wang, Xi Li, Xuehai Zhou. FPGA implementation of a scheduler supporting parallel dataflow execution. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 1216-1219, IEEE, 2013. [doi]
@inproceedings{ZhangWLZ13,
title = {FPGA implementation of a scheduler supporting parallel dataflow execution},
author = {Junneng Zhang and Chao Wang and Xi Li and Xuehai Zhou},
year = {2013},
doi = {10.1109/ISCAS.2013.6572071},
url = {http://dx.doi.org/10.1109/ISCAS.2013.6572071},
researchr = {https://researchr.org/publication/ZhangWLZ13},
cites = {0},
citedby = {0},
pages = {1216-1219},
booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013},
publisher = {IEEE},
isbn = {978-1-4673-5760-9},
}