A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips

Lei Zhang, Jianxun Yang, Chengbo Xue, Yue Ma, Shan Cao. A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]

Abstract

Abstract is missing.