A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps - researchr publication authors

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Zhao Zhang, Guang Zhu, C. Patrick Yue. A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 158, IEEE, 2019. [doi]

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