Zhao Zhang, Guang Zhu, C. Patrick Yue. A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 158, IEEE, 2019. [doi]
@inproceedings{ZhangZY19-11,
title = {A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps},
author = {Zhao Zhang and Guang Zhu and C. Patrick Yue},
year = {2019},
doi = {10.23919/VLSIC.2019.8778061},
url = {https://doi.org/10.23919/VLSIC.2019.8778061},
researchr = {https://researchr.org/publication/ZhangZY19-11},
cites = {0},
citedby = {0},
pages = {158},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}