An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige D. Varadarajan. An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. J. Solid-State Circuits, 34(11):1564-1570, 1999. [doi]

@article{ZhaoBDKLNNSV99,
  title = {An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin},
  author = {Cangsang Zhao and Uddalak Bhattacharya and Martin Denham and Jim Kolousek and Yi Lu and Yong-Gee Ng and Novat Nintunze and Kamal Sarkez and Hemmige D. Varadarajan},
  year = {1999},
  doi = {10.1109/4.799864},
  url = {https://doi.org/10.1109/4.799864},
  researchr = {https://researchr.org/publication/ZhaoBDKLNNSV99},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {34},
  number = {11},
  pages = {1564-1570},
}