Xiaoteng Zhao, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap., 68(1):89-102, 2021. [doi]
@article{ZhaoCMM21,
title = {A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS},
author = {Xiaoteng Zhao and Yong Chen 0005 and Pui-In Mak and Rui Paulo Martins},
year = {2021},
doi = {10.1109/TCSI.2020.3038865},
url = {https://doi.org/10.1109/TCSI.2020.3038865},
researchr = {https://researchr.org/publication/ZhaoCMM21},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. I Regul. Pap.},
volume = {68},
number = {1},
pages = {89-102},
}