Ziwei Zhao, Fei Wang 0036, Qi Ni. An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points. In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. pages 1-4, IEEE, 2019. [doi]
@inproceedings{ZhaoWN19-0,
title = {An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points},
author = {Ziwei Zhao and Fei Wang 0036 and Qi Ni},
year = {2019},
doi = {10.1109/ASICON47005.2019.8983656},
url = {https://doi.org/10.1109/ASICON47005.2019.8983656},
researchr = {https://researchr.org/publication/ZhaoWN19-0},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019},
publisher = {IEEE},
isbn = {978-1-7281-0735-6},
}