Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs - researchr publication authors

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Wei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura. Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. In IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013. pages 1-4, IEEE, 2013. [doi]

This author has not been identified. Look up 'Wei Zhong' in GoogleThis author has not been identified. Look up 'Song Chen' in GoogleThis author has not been identified. Look up 'Yang Geng' in GoogleThis author has not been identified. Look up 'Takeshi Yoshimura' in Google

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