A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS

Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan 0002. A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. In IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, June 16-20, 2024. pages 1-2, IEEE, 2024. [doi]

Abstract

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