Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao. A High Reliability FPGA Chip Identification Generator Based on PDLs. In 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018. pages 63-67, IEEE, 2018. [doi]
@inproceedings{ZhouLJHYXY18,
title = {A High Reliability FPGA Chip Identification Generator Based on PDLs},
author = {Kai Zhou and Huaguo Liang and Yue Jiang and Zhengfeng Huang and Maoxiang Yi and Xiumin Xu and Yao Yao},
year = {2018},
doi = {10.1109/ATS.2018.00023},
url = {https://doi.org/10.1109/ATS.2018.00023},
researchr = {https://researchr.org/publication/ZhouLJHYXY18},
cites = {0},
citedby = {0},
pages = {63-67},
booktitle = {27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9466-4},
}