A method to speed up VLSI hierarchical physical design in floorplanning

Yanling Zhou, Yunyao Yan, Wei Yan. A method to speed up VLSI hierarchical physical design in floorplanning. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 347-350, IEEE, 2017. [doi]

Abstract

Abstract is missing.