A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit - researchr publication authors

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Jiafeng Zhu, Na Bai, Jianhui Wu. A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit. Microelectronics Journal, 44(4):283-291, 2013. [doi]

This author has not been identified. Look up 'Jiafeng Zhu' in GoogleThis author has not been identified. Look up 'Na Bai' in GoogleThis author has not been identified. Look up 'Jianhui Wu' in Google

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