Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng Yeo, Zhi-Hui Kong. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Trans. VLSI Syst., 18(8):1225-1229, 2010. [doi]
@article{ZhuGZYK10,
title = {Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing},
author = {Ning Zhu and Wang Ling Goh and Weija Zhang and Kiat Seng Yeo and Zhi-Hui Kong},
year = {2010},
doi = {10.1109/TVLSI.2009.2020591},
url = {http://dx.doi.org/10.1109/TVLSI.2009.2020591},
tags = {design},
researchr = {https://researchr.org/publication/ZhuGZYK10},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {18},
number = {8},
pages = {1225-1229},
}