Haotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang. A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs. In 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017. pages 1-6, IEEE, 2017. [doi]
Abstract is missing.