Abstract is missing.
- Fault-tolerant routing methodology for Networks-on-ChipS. Savva. 1-3 [doi]
- Pulse controlled memristor-based delay elementThanasin Bunnam, Ahmed Soltan, Danil Sokolov, Alex Yakovlev. 1-8 [doi]
- Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICsLeonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen. 1-8 [doi]
- Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold levelEsteve Amat, Antonio Calomarde, Ramon Canal, A. Rubio. 1-6 [doi]
- Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technologyAlfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini. 1-8 [doi]
- μDMA: An autonomous I/O subsystem for IoT end-nodesAntonio Pullini, Davide Rossi, Germain Haugou, Luca Benini. 1-8 [doi]
- Optical sensor process variability in a 0.18 μm high voltage CMOS technologyFrederic Roger, Anderson Pires Singulani, Jong Mun Park. 1-6 [doi]
- Rapid power-management exploration using post-processing of the system-level simulation resultsDominik Macko. 1-6 [doi]
- Parallelization and energy evaluation of interframe compression technique for video images - QSDPCMPanagiotis N. Smyrlis, Dimosthenis C. Tsouros, Minas Dasygenis. 1-8 [doi]
- An analytical delay model for ReRAM memory cellsCarol de Benito, Mohamed Moner Al Chawa, Josep L. Rosselló, Miquel Roca, Rodrigo Picos, Ioannis Messaris, Spiridon Nikolaidis. 1-6 [doi]
- Edge effect aware crosstalk avoidance technique for 3D integrationLennart Bamberg, Amir Najafi, Alberto García Ortiz. 1-8 [doi]
- Empirical CPU power modelling and estimation in the gem5 simulatorBasireddy Karunakar Reddy, Matthew J. Walker, Domenico Balsamo, Stephan Diestelhorst, Bashir M. Al-Hashimi, Geoff V. Merrett. 1-8 [doi]
- A fair comparison of adders in stochastic regimeArdalan Najafi, Moritz Weisbrich, Guillermo Payá Vayá, Alberto García Ortiz. 1-6 [doi]
- Approximate adder segmentation technique and significance-driven error correctionKhaled Al-Maaitah, Ghaith Tarawneh, Ahmed Soltan, Issa Qiqieh, Alex Yakovlev. 1-6 [doi]
- FLINT+: A runtime-configurable emulation-based stochastic timing analysis frameworkMoritz Weisbrich, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, A. Najafi, Alberto García Ortiz. 1-8 [doi]
- Energy aware Networks-on-Chip cortex inspired communicationErwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi. 1-8 [doi]
- Variability and sensitivity to process parameters variations in InGaAs dual-gate ultra-thin body MOSFETs: A scaling perspectiveNicolo Zagni, Francesco Maria Puglisi, Giovanni Verzellesi, Paolo Pavan. 1-5 [doi]
- Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistorLotta Romhildt, Felix Zorgiebel, Bergoi Ibarlucea, Maryam Vahdatzadeh, Larysa Baraban, Gianaurelio Cuniberti, Sebastian Pregl, Walter M. Weber, Thomas Mikolajick, Jörg Opitz. 1-4 [doi]
- Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVsStylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos. 1-6 [doi]
- 3D-IC signal TSV assignment for thermal and wirelength optimizationYuxin Qian, Cong Hao, Takeshi Yoshimura. 1-8 [doi]
- A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETsHaotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang. 1-6 [doi]
- High voltage recycling scheme to improve power consumption of regulated charge pumpsSteve Ngueya W., Julien Mellier, Stephane Ricard, Jean Michel Portal, Hassen Aziza. 1-5 [doi]
- Optimal content-dependent dynamic brightness scaling for OLED displaysDaniele Jahier Pagliari, Enrico Macii, Massimo Poncino. 1-6 [doi]
- From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructureDimosthenis Masouros, Ioannis Bakolas, Vasileios Tsoutsouras, Kostas Siozios, Dimitrios Soudris. 1-6 [doi]
- User dependent aging prediction model for automotive controllers with power electronicsSunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel. 1-6 [doi]
- Capacitive adiabatic logic based on gap-closing MEMS devicesAyrat Galisultanov, Yann Perrin, Hatem Samaali, Louis Hutin, Hervé Fanet, Philippe Basset, Gaël Pillonnet. 1-6 [doi]
- Timing modeling at RT-level by separation of design- and stress related aging impactsNils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel. 1-6 [doi]
- Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variationsHimadri Singh Raghav, Vivian A. Bartlett, Izzet Kale. 1-8 [doi]
- High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standardNikolaos Kefalas, George Theodoridis. 1-8 [doi]
- 3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-ChipKonstantinos Tatas, S. Savva, Costas Kyriacou. 1-8 [doi]
- Prototyping memristors in digital system with an FPGA-based testing environmentDaniel Wust, Mehrdad Biglari, Johannes Kncodtel, Marc Reichenbach, Christopher Söll, Dietmar Fey. 1-7 [doi]
- Parasitic effects on memristive logic architectureXiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir. 1-5 [doi]
- Architecture exploration of a fixed point computation unit using precise timing spiking neuronsThomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné. 1-8 [doi]
- Evaluation and analysis of single-phase clock flip-flops for NTV applicationsYunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski. 1-6 [doi]
- Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applicationsPasquale Davide Schiavone, Francesco Conti 0001, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini. 1-8 [doi]
- 1-D memristor-based cellular automaton for pseudo-random number generationRafailia-Eleni Karamani, Vasileios G. Ntinas, Ioannis Vourkas, Georgios Ch. Sirakoulis. 1-6 [doi]
- Memristive logic: A framework for evaluation and comparisonJohn Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky. 1-8 [doi]
- A substrate noise reduction methodology based on power domain separation of GALS subcomponentsMilan Babic, Milos Krstic. 1-6 [doi]
- Placement-based SER estimation in the presence of multiple faults in combinational logicGeorgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor E. Evmorfopoulos, George Dimitriou, Georgios I. Stamoulis. 1-6 [doi]
- On the origin of the fading memory effect in ReRAMsStephan Menzel, Rainer Waser, Anne Siemon, C. La Torre, M. Schulten, Rainer Waser, Alon Ascoli, Ronald Tetzlaff. 1-5 [doi]
- Power proportional adder design for Internet of Things in a 65 nm processAdrian Wheeldon, Jordan Morris, Danil Sokolov, Alex Yakovlev. 1-6 [doi]
- Failure probability of a FinFET-based SRAM cell utilizing the most probable failure pointMichail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris. 1-8 [doi]
- Analytical hold timing fixing for sub-threshold circuit based on its lognormal distributionJingjing Guo, Min Wang, Jizhe Zhu, Xinning Liu, Jun Yang. 1-8 [doi]
- Memristive two-portsDalibor Biolek, Zdenek Biolek, Viera Biolkova. 1-4 [doi]
- An FPGA-based thermal emulation framework for multicore systemsMd Shahidul Alam, Alberto García Ortiz. 1-6 [doi]
- Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysisLei Li, Michael Gautschi, Luca Benini. 1-8 [doi]
- Modeling energy-performance tradeoffs in ARM big.LITTLE architecturesEvangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis. 1-8 [doi]
- Effect of supply voltage on random telegraph noise of transistors under switching conditionIslam A. K. M. Mahfuzul, Hidetoshi Onodera. 1-8 [doi]