SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor

Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng. SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electronic Express, 14(8):20170218, 2017. [doi]

Abstract

Abstract is missing.