A low-power all-digital PLL architecture based on phase prediction

Jingcheng Zhuang, Robert Bogdan Staszewski. A low-power all-digital PLL architecture based on phase prediction. In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012. pages 797-800, IEEE, 2012. [doi]

Abstract

Abstract is missing.