Abstract is missing.
- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache BlocksThiago Baldissera Biazus, Mateus Beck Rutzig. 3-14 [doi]
- A Vector Caching Scheme for Streaming FPGA SpMV AcceleratorsYaman Umuroglu, Magnus Jahre. 15-26 [doi]
- Hierarchical Dynamic Power-Gating in FPGAsRehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas. 27-38 [doi]
- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression CompilationIan Graves, Adam M. Procter, William L. Harrison, Michela Becchi, Gerard Allwein. 41-52 [doi]
- ArchHDL: A Novel Hardware RTL Design Environment in C++Shimpei Sato, Kenji Kise. 53-64 [doi]
- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGAZaid Al-Khatib, Samar Abdi. 65-76 [doi]
- Preemptive Hardware Multitasking in ReconOSMarkus Happe, Andreas Traber, Ariane Keller. 79-90 [doi]
- A Fully Parallel Particle Filter Architecture for FPGAsFynn Schwiegelshohn, Eugen Ossovski, Michael Hübner. 91-102 [doi]
- TEAChER: TEach AdvanCEd Reconfigurable Architectures and ToolsKostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker. 103-114 [doi]
- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator ArchitecturesDionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris. 117-128 [doi]
- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAsLuca Sterpone, Boyang Du. 129-140 [doi]
- Advanced SystemC Tracing and Analysis Framework for Extra-Functional PropertiesPhilipp A. Hartmann, Kim Grüttner, Wolfgang Nebel. 141-152 [doi]
- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable ComponentsXerach Peña, Fernando Rincón, Julio Dondo, Julian Caba, Juan Carlos López. 153-164 [doi]
- Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate ArraysMichael Metzner, Jesus Lizarraga, Christophe Bobda. 167-178 [doi]
- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-ChipPhilipp Gorski, Tim Wegner, Dirk Timmermann. 179-190 [doi]
- Survey on Real-Time Network-on-Chip ArchitecturesSalma Hesham, Jens Rettkowski, Diana Göhringer, Mohamed A. Abd El ghany. 191-202 [doi]
- Efficient SR-Latch PUFBilal Habib, Jens-Peter Kaps, Kris Gaj. 205-216 [doi]
- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case StudyEkawat Homsirikamol, Kris Gaj. 217-228 [doi]
- Dual CLEFIA/AES Cipher Core on FPGAJoão Carlos Resende, Ricardo Chaves. 229-240 [doi]
- An Efficient and Flexible FPGA Implementation of a Face Detection SystemHichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink. 243-254 [doi]
- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive ContextJens Rettkowski, Philipp Wehner, Marc Schülper, Diana Göhringer. 255-266 [doi]
- A Dynamically Reconfigurable Mixed Analog-Digital Filter BankHiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao. 267-279 [doi]
- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAsTobias Strauch. 280-290 [doi]
- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable ArchitecturesAnupam Chattopadhyay, Xiaolin Chen. 293-300 [doi]
- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRAZoltán Endre Rákossy, Dominik Stengele, Axel Acosta Aponte, Saumitra Chafekar, Paolo Bientinesi, Anupam Chattopadhyay. 301-310 [doi]
- A Novel Concept for Adaptive Signal Processing on Reconfigurable HardwarePeter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker. 311-320 [doi]
- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC ArchitecturesEfstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos. 321-330 [doi]
- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced EffectsLucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda Lima Kastensmidt, Giovanni Bruni, Christopher Frost. 331-338 [doi]
- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience ExperimentsPaulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets. 339-348 [doi]
- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based SystemsRen Chen, Viktor K. Prasanna. 349-356 [doi]
- Acceleration of Data Streaming Classification using Reconfigurable TechnologyPavlos Giakoumakis, Grigorios Chrysos, Apostolos Dollas, Ioannis Papaefstathiou. 357-364 [doi]
- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware ApproachTobias Wiersema, Sen Wu, Marco Platzner. 365-372 [doi]
- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh PlatformMansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul. 373-382 [doi]
- A Challenge of Portable and High-Speed FPGA AcceleratorTakuma Usui, Ryohei Kobayashi, Kenji Kise. 383-392 [doi]
- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate ArrayRetsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara. 393-400 [doi]
- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor ArchitectureStephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume. 401-410 [doi]
- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect OptimizationSonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid. 411-418 [doi]
- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation CostErnesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Wang Jiang Chau. 419-426 [doi]
- A Flexible Multilayer Perceptron Co-processor for FPGAsZeyad Aklah, David Andrews. 427-434 [doi]
- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCsMaikon A. F. Bueno, Carlos R. P. Almeida Jr., José A. M. de Holanda, Eduardo Marques. 435-442 [doi]
- Towards Performance Modeling of 3D Memory Integrated FPGA ArchitecturesShreyas G. Singapura, Anand V. Panangadan, Viktor K. Prasanna. 443-450 [doi]
- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDLShinya Takamaeda-Yamazaki. 451-460 [doi]
- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale ComputingToshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato. 463-474 [doi]
- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable PlatformsGeorge Lentaris, Ioannis Stamoulias, Dionysios Diamantopoulos, Konstantinos Maragos, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez, Manolis I. A. Lourakis, Xenophon Zabulis, Ioannis Kostavelis, Lazaros Nalpantidis, Evangelos Boukas, Antonios Gasteratos. 475-486 [doi]
- Hardware Task Scheduling for Partially Reconfigurable FPGAsGeorge Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos. 487-498 [doi]
- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and MonitoringVasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris, Leonidas Lymperopoulos. 499-510 [doi]
- DynamIA: Dynamic Hardware Reconfiguration in Industrial ApplicationsNele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno da Silva, Abdellah Touhafi, Alois Kern, Stephan Knappmann, Jens Rettkowski, Muhammed Al Kadi, Diana Göhringer, Michael Hübner. 513-518 [doi]
- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO PerspectiveChristos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Diana Göhringer, Maria Dagioglou, Theodoros Giannakopoulos, Stasinos Konstantopoulos, Vangelis Karkaletsis. 519-530 [doi]
- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE ApproachAndreas Raptopoulos, Sotirios Xydis, Dimitrios Soudris. 531-541 [doi]
- COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS SimulatorIoannis Papaefstathiou, Gregory Chrysos, Lambros Sarakis. 542-553 [doi]