Abstract is missing.
- Improving the Performance of Adaptive Cache in Reconfigurable VLIW ProcessorSensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang. 3-15 [doi]
- 1IP Architecture Using Partial ReconfigurationÁlvaro Avelino, Valentin Obac Roda, Naim Harb, Carlos Valderrama, Glauberto Albuquerque, Paulo Da Cunha Possa. 16-27 [doi]
- NIM: An HMC-Based Machine for Neuron ComputationGeraldo F. Oliveira, Paulo C. Santos, Marco Antonio Zanata Alves, Luigi Carro. 28-35 [doi]
- VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging ApplicationsJoost Hoozemans, Rolf Heij, Jeroen van Straten, Zaid Al-Ars. 36-43 [doi]
- Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on ChipChristophe Bobda, Joshua Mead, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat. 47-59 [doi]
- Rapid Development of Gzip with MaxJNils Voss, Tobias Becker, Oskar Mencer, Georgi Gaydadjiev. 60-71 [doi]
- On the Use of (Non-)Cryptographic Hashes on FPGAsAndreas Fiessler, Daniel Loebenberger, Sven Hager, Björn Scheuermann. 72-80 [doi]
- An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing ApplicationsNgoc Hung Nguyen, Sheraz Ali Khan, Cheol Hong Kim, Jong Myon Kim. 81-89 [doi]
- Soft Timing Closure for Soft Programmable Logic Cores: The ARGen ApproachTheotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann, Pierre Guilloux. 93-105 [doi]
- FPGA Debugging with MATLAB Using a Rule-Based Inference SystemHabib ul Hasan Khan, Diana Göhringer. 106-117 [doi]
- Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based DesignsAbdul Rafay Khatri, Ali Hayek, Josef Börcsök. 118-128 [doi]
- A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable ArchitecturesMuhammad Adeel Pasha, Umer Farooq, Muhammad Ali, Bilal Siddiqui. 129-137 [doi]
- Parameter Sensitivity in Virtual FPGA ArchitecturesPeter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker. 141-153 [doi]
- Custom Framework for Run-Time Trading StrategiesAndreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon. 154-167 [doi]
- Exploring HLS Optimizations for Efficient Stereo Matching Hardware ImplementationKarim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser. 168-176 [doi]
- Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available PowerDimple Sharma, Victor Dumitriu, Lev Kirischian. 177-186 [doi]
- Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoCÁdria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt. 189-201 [doi]
- Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAsAndré Flores dos Santos, Lucas Antunes Tambara, Fabio Benevenuti, Jorge Tonfat, Fernanda Lima Kastensmidt. 202-213 [doi]
- FPGA Applications in Unmanned Aerial Vehicles - A ReviewMustapha Bouhali, Farid Shamani, Zine Elabadine Dahmane, Abdelkader Belaidi, Jari Nurmi. 217-228 [doi]
- Genomic Data Clustering on FPGAs for CompressionEnrico Petraglio, Rick Wertenbroek, Flavio Capitao, Nicolas Guex, Christian Iseli, Yann Thoma. 229-240 [doi]
- A Quantitative Analysis of the Memory Architecture of FPGA-SoCsMatthias Göbel, Ahmed Elhossini, Chi Ching Chi, Mauricio Alvarez Mesa, Ben H. H. Juurlink. 241-252 [doi]
- Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA PlatformsRuizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu. 255-267 [doi]
- An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron PruningTomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura. 268-280 [doi]
- Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point ArithmeticRuochun Jin, Jingfei Jiang, Yong Dou. 281-288 [doi]
- FPGA Implementation of a Short Read Mapping AcceleratorMostafa Morshedi, Hamid Noori. 289-296 [doi]
- dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAsPaul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk. 299-310 [doi]
- A Machine Learning Methodology for Cache RecommendationOsvaldo Navarro, Jones Yudi Mori, Javier Hoffmann, Fabian Stuckmann, Michael Hübner. 311-322 [doi]
- ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality TestJan Macheta, Agnieszka Dabrowska-Boruch, Pawel Russek, Kazimierz Wiatr. 323-330 [doi]