Abstract is missing.
- Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar ImagingHelena Cruz, Rui Policarpo Duarte, Horácio C. Neto. 3-16 [doi]
- Optimizing CNN-Based Hyperspectral Image Classification on FPGAsShuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk. 17-31 [doi]
- Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache ArrowJohan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars. 32-47 [doi]
- A Novel Encoder for TDCsGünter Knittel. 48-57 [doi]
- A Resource Reduced Application-Specific FPGA SwitchQian Zhao 0001, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida. 58-67 [doi]
- Software-Defined FPGA Accelerator Design for Mobile Deep Learning ApplicationsPanagiotis G. Mousouliotis, Loukas P. Petrou. 68-77 [doi]
- Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task SchedulingBruno da Silva, An Braeken, Abdellah Touhafi. 81-95 [doi]
- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational SystemsTobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker. 96-111 [doi]
- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAsKenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler. 112-126 [doi]
- Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware TrojanQazi Arbab Ahmed, Tobias Wiersema, Marco Platzner. 127-136 [doi]
- Secure Local Configuration of Intellectual Property Without a Trusted Third PartyNadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker. 137-146 [doi]
- HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image ProcessingLester Kalms, Ariel Podlubne, Diana Göhringer. 149-164 [doi]
- Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video StreamPiotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka, Tomasz Kryjak. 165-180 [doi]
- A Scalable FPGA-Based Architecture for Depth Estimation in SLAMKonstantinos Boikos, Christos-Savvas Bouganis. 181-196 [doi]
- Evaluating LULESH Kernels on OpenCL FPGAZheming Jin, Hal Finkel. 199-213 [doi]
- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing SystemsJens Korinth, Jaco Hofmann, Carsten Heinz, Andreas Koch 0001. 214-229 [doi]
- Graph-Based Code Restructuring Targeting HLS for FPGAsAfonso Canas Ferreira, João M. P. Cardoso. 230-244 [doi]
- UltraSynth: Integration of a CGRA into a Control Engineering EnvironmentDennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel 0003, Andreas Koch 0001. 247-261 [doi]
- Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked MemoriesJoão Paulo C. de Lima, Paulo C. Santos, Rafael Fao de Moura, Marco Antonio Zanata Alves, Antonio C. S. Beck, Luigi Carro. 262-276 [doi]
- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic AlgorithmsAndré Werner, Florian Fricke, Keyvan Shahin, Florian Werner 0002, Michael Hübner. 277-291 [doi]
- ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable ArchitecturesLudovica Bozzoli, Luca Sterpone. 295-304 [doi]
- Update or Invalidate: Influence of Coherence Protocols on Configurable HW AcceleratorsJohanna Rohde, Lukas Johannes Jung, Christian Hochberger. 305-316 [doi]
- Hybrid Prototyping for Manycore Design and ValidationLeonard Masing, Fabian Lesniak, Jürgen Becker. 319-333 [doi]
- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous TasksUmar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis. 334-349 [doi]
- Third Party CAD Tools for FPGA Design - A Survey of the Current LandscapeBrent E. Nelson. 353-367 [doi]
- Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic SegmentationMasayuki Shimoda, Youki Sada, Hiroki Nakahara. 371-386 [doi]
- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAsAna Gonçalves, Tiago Peres, Mário P. Véstias. 387-401 [doi]
- Faster Convolutional Neural Networks in Low Density FPGAs Using Block PruningTiago Peres, Ana Gonçalves, Mário P. Véstias. 402-416 [doi]