Abstract is missing.
- High-Level Synthesis of Memory Systems for Decoupled Data OrchestrationMasayuki Usui, Shinya Takamaeda-Yamazaki. 3-18 [doi]
- Rapid Prototyping of Complex Micro-architectures Through High-Level SynthesisSara Sadat Hoseininasab, Caroline Collange, Steven Derrien. 19-34 [doi]
- NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAsSajjad Tamimi, Arthur Bernhardt, Florian Stock, Ilia Petrov 0001, Andreas Koch 0001. 35-50 [doi]
- On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAsPanagiotis Mousouliotis, Topi Leppänen, Pekka Jääskeläinen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros. 51-65 [doi]
- Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICEJonas Gehrunger, Christian Hochberger. 66-80 [doi]
- Memory-Aware Scheduling for a Resource-Elastic FPGA Operating SystemShaden M. Alismail, Dirk Koch. 81-96 [doi]
- ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision ArchitecturesLester Kalms, Matthias Nickel, Diana Göhringer. 97-112 [doi]
- FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query ProcessingVitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake. 115-130 [doi]
- Accelerating Graph Neural Networks in Pytorch with HLS and Deep DataflowsJosé L. Núñez-Yáñez. 131-145 [doi]
- DNN Model Theft Through Trojan Side-Channel on Edge FPGA AcceleratorSrivatsan Chandrasekar, Siew Kei Lam, Srikanthan Thambipillai. 146-158 [doi]
- Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA ImplementationsEvangelia Konstantopoulou, George Athanasiou, Nicolas Sklavos 0001. 159-172 [doi]
- A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II ExperimentKai Lukas Unger, Jürgen Becker 0001, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart. 173-184 [doi]
- On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural DecodingGianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni. 185-199 [doi]
- Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGAMaciej Baczmanski, Mateusz Wasala, Tomasz Kryjak. 200-211 [doi]
- Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoCGeorge Pagonis, Vasileios Leon, Dimitrios Soudris, George Lentaris. 215-229 [doi]
- Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM ArchitectureRafael Fão de Moura, Luigi Carro. 230-244 [doi]
- 64Lennart Clausing, Zakarya Guettatfi, Paul Kaufmann, Christian Lienen, Marco Platzner. 245-259 [doi]
- Evolutionary FPGA-Based Spiking Neural Networks for Continual LearningAndrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez. 260-274 [doi]
- More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation CodingAlexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach. 275-289 [doi]
- Energy Efficient DNN Compaction for Edge DeploymentBijin Elsa Baby, Dipika Deb, Benuraj Sharma, Kirthika Vijayakumar, Satyajit Das. 290-303 [doi]
- TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAsJohannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Marc Reichenbach. 307-321 [doi]
- An Almost Fully RRAM-Based LUT Design for Reconfigurable CircuitsPhilipp Grothe, Saleh Mulhem, Mladen Berekovic. 322-337 [doi]
- A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGATakeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara. 338-353 [doi]
- Radiation Tolerant Reconfigurable Hardware Architecture Design MethodologyEike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá. 357-360 [doi]
- A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed TomographyDaniele Passaretti, Thilo Pionteck. 361-365 [doi]
- Simulation and Modelling for Network-on-Chip Based MPSoCJulian Haase, Diana Göhringer. 366-370 [doi]
- A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable ComputingSafdar Mahmood, Michael Hübner 0001, Marc Reichenbach. 371-374 [doi]