Abstract is missing.
- Synchronous Latency Insensitive DesignChrister Svensson. 3 [doi]
- A Fast and Energy-Efficient StackJo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins. 7-16 [doi]
- Static Tokens: Using Dataflow to Automate Concurrent Pipeline SynthesisJohn Teifel, Rajit Manohar. 17-27 [doi]
- General Testers for Asynchronous CircuitsRadu Negulescu. 28-38 [doi]
- Analog Micropipeline Rings for High Precision TimingScott Fairbanks, Simon W. Moore. 41-50 [doi]
- Transistor Sizing: How to Control the Speed and Energy Consumption of a CircuitJo C. Ebergen, Jonathan Gainsley, Paul Cunningham. 51-61 [doi]
- Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive ModelMasashi Imai, Metehan Özcan, Takashi Nanya. 62-71 [doi]
- Non-Uniform Access Asynchronous Register FilesDavid Fang, Rajit Manohar. 75-85 [doi]
- Phase Alignment Using Asynchronous State MachinesAlireza Kaviani. 86-94 [doi]
- High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard CellsMarcos Ferretti, Recep O. Ozdag, Peter A. Beerel. 95-105 [doi]
- Contacting Biological Cells with Electronic CircuitsMartin Jenkner. 109 [doi]
- Bolstering Faith in GasP Circuits through Formal VerificationXiaohua Kong, Radu Negulescu. 113-124 [doi]
- A General Purpose Behavioural Asynchronous Synthesis SystemMathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton. 125-134 [doi]
- Synthesis of Speed Independent Circuits Based on DecompositionTomohiro Yoneda, Hiroomi Onda, Chris J. Myers. 135-145 [doi]
- Handshake Protocols for De-SynchronizationIvan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou. 149-158 [doi]
- Hiding Synchronization Delays in a GALS Processor MicroarchitectureGreg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas. 159-169 [doi]
- Data Synchronization Issues in GALS SoCsRostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou. 170-180 [doi]
- Bringing Handshake Technology to the Open MarketAd M. G. Peeters. 183 [doi]
- A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI TemplatesRecep O. Ozdag, Peter A. Beerel. 187-197 [doi]
- Asynchronous FIR Filters: Towards a New Digital Processing ChainF. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin. 198-206 [doi]
- An Asynchronous, Iterative Implementation of the Original Booth Multiplication AlgorithmAristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury. 207-215 [doi]
- High-Speed Reduced Stack Dual Lock CircuitsNisrine Saadallah, Xiaohua Kong, Radu Negulescu. 219-228 [doi]
- An Eight-Bit Divider Implemented in Asynchronous Pulse LogicMika Nyström, Elaine Ou, Alain J. Martin. 229-239 [doi]
- Long Wires and Asynchronous ControlRon Ho, Jonathan Gainsley, Robert J. Drost. 240-249 [doi]