Abstract is missing.
- Deep Pipelines vs. Risk and Power WallsRobert P. Colwell.
- New Prospects for Clocking Synchronous and Quasi-Asynchronous SystemsPhillip Restle, Kenneth L. Shepard.
- Proximity Communication and TimeRobert J. Drost, Ivan E. Sutherland.
- Energy Efficient SurfingSuwen Yang, Brian D. Winters, Mark R. Greenstreet. 2-11 [doi]
- GasP Control for Domino CircuitsJo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland. 12-22 [doi]
- Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode LogicTin Wai Kwan, Maitham Shams. 23-32 [doi]
- A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-ChipTobias Bjerregaard, Jens Sparsø. 34-43 [doi]
- An Asynchronous Router for Multiple Service Levels Networks on ChipRostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar. 44-53 [doi]
- An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design FrameworkEdith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin. 54-63 [doi]
- Register Communication between Mutually Asynchronous DomainsJoep L. W. Kessels. 66-75 [doi]
- Request-Driven GALS Technique for Wireless Communication SystemMilos Krstic, Eckhard Grass, Christian Stahl. 76-85 [doi]
- Self-Timed Circuitry for Global ClockingScott Fairbanks, Simon W. Moore. 86-96 [doi]
- Modeling and Verifying Circuits Using Generalized Relative TimingSanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens. 98-108 [doi]
- Controlling Event Spacing in Self-Timed RingsVassilis Zebilis, Christos P. Sotiriou. 109-115 [doi]
- Delay Insensitive Encoding and Power Analysis: A Balancing ActKonrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald. 116-125 [doi]
- A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth MultiplierJustin Hensley, Anselmo Lastra, Montek Singh. 128-137 [doi]
- Continuous-Time Digital Signal ProcessorsYee William Li, Kenneth L. Shepard, Yannis P. Tsividis. 138-143 [doi]
- BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous ProcessorVirantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar. 144-154 [doi]
- SEU-Tolerant QDI CircuitsWonjin Jang, Alain J. Martin. 156-165 [doi]
- A Multiplexor Based Test Method for Self-Timed CircuitsFrank te Beest, Ad M. G. Peeters. 166-175 [doi]
- High Level Synthesis of Timed Asynchronous CircuitsTomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers. 178-189 [doi]
- Behavior and Synthesis of Two-Input Gate Asynchronous CircuitsNikolai Starodoubtsev, Sergei Bystrov. 190-200 [doi]
- A Unified Coding Framework for Delay-InsensitivityFrederic Worm, Patrick Thiran, Paolo Ienne. 201-211 [doi]