Abstract is missing.
- ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System ArchitectureJean-Pierre Schoellkopf. [doi]
- Asynchronous Design: An Enabler for Flexible MicroelectronicsNobuo Karaki. [doi]
- Asynchronous Architectures for Nanometer ScalesFerdinand Peper. [doi]
- Measuring Deep MetastabilityDavid Kinniment, Keith Heron, Gordon Russell. 2-11 [doi]
- A Level-Crossing Flash Asynchronous Analog-to-Digital ConverterFilipp Akopyan, Rajit Manohar, Alyssa B. Apsel. 12-22 [doi]
- An Asynchronous High-Throughput Control Circuit For Proximity CommunicationJo C. Ebergen, Alex Chow, Bill Coates, Justin Schauer, David Hopkins. 23-33 [doi]
- Self-Healing Asynchronous ArraysSong Peng, Rajit Manohar. 34-45 [doi]
- Low-Overhead Testing of Delay Faults in High-Speed Asynchronous PipelinesGennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris. 46-56 [doi]
- A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous PipelinesFeng Shi, Yiorgos Makris. 57-67 [doi]
- A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay VariationsMasashi Imai, Takashi Nanya. 68-77 [doi]
- An ultra-low energy asynchronous processor for Wireless Sensor NetworksL. Necchi, Luciano Lavagno, Davide Pandini, Laura Vanzago. 78-85 [doi]
- AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic AdaptationD. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin. 86-97 [doi]
- Surfing InterconnectMark R. Greenstreet, Jihong Ren. 98-106 [doi]
- Multiple-Rail Phase-Encoding for NoCCrescenzo D Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Oleg V. Maevsky. 107-116 [doi]
- Fast Asynchronous Shift Register for Bit-Serial CommunicationRostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny. 117-127 [doi]
- Optimal Technology Mapping and Cell Merger for Asynchronous Threshold NetworksCheoljoo Jeong, Steven M. Nowick. 128-137 [doi]
- Synthesising Heterogeneously Encoded SystemsW. B. Toms, David A. Edwards, Andrew Bardsley. 138-149 [doi]
- GALS at ETH Zurich: Success or FailureFrank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. 150-159 [doi]
- Interface Design for Rationally Clocked GALS SystemsJoycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan. 160-171 [doi]
- Design of On-chip and Off-chip Interfaces for a GALS NoC ArchitectureEdith Beigné, Pascal Vivet. 172-183 [doi]
- Slack Matching Asynchronous DesignsPeter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies. 184-194 [doi]
- Slack Matching Quasi Delay-Insensitive CircuitsPiyush Prakash, Alain J. Martin. 195-204 [doi]